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Datasheet: NCP1207-D (ON Semiconductor)

Pwm Current-mode Controller For Free Running Quasi-resonant Operation

 

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ON Semiconductor
Semiconductor Components Industries, LLC, 2004
June, 2004 - Rev. 6
1
Publication Order Number:
NCP1207/D
NCP1207
PWM Current-Mode
Controller for Free Running
Quasi-Resonant Operation
The NCP1207 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi-Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 8.0
ms
timer prevents the free-run frequency to exceed 100 kHz (therefore
below the 150 kHz CISPR-22 EMI starting limit), while the skip
adjustment capability lets the user select the frequency at which the
burst foldback takes place.
The Dynamic Self-Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1207. This feature is particularly useful in applications
where the output voltage varies during operation (e.g. battery
chargers). Due to its high-voltage technology, the IC is directly
connected to the high-voltage DC rail. As a result, the short-circuit
trip point is not dependent upon any V
CC
auxiliary level.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin, also enables fast
Overvoltage Protection (OVP). Once an OVP has been detected, the
IC permanently latches-off.
Finally, the continuous feedback signal monitoring implemented
with an overcurrent fault protection circuitry (OCP) makes the final
design rugged and reliable.
Features
Free-Running Borderline/Critical Mode Quasi-Resonant Operation
Current-Mode with Adjustable Skip-Cycle Capability
No Auxiliary Winding V
CC
Operation
Auto-Recovery Overcurrent Protection
Latching Overvoltage Protection
External Latch Triggering, e.g. Via Overtemperature Signal
500 mA Peak Current Source/Sink Capability
Internal 1.0 ms Soft-Start
Internal 8.0
ms Minimum T
OFF
Adjustable Skip Level
Internal Temperature Shutdown
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
Pb-Free Package is Available
Typical Applications
AC/DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set-Top Boxes, TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
PDIP-8
N SUFFIX
CASE 626
1
8
1
8
SOIC-8
D1, D2 SUFFIX
CASE 751
1
8
5
3
4
(Top View)
DMG
CS
HV
PIN CONNECTIONS
7
6
2
NC
FB
GND
Drv
V
CC
MARKING
DIAGRAMS
1207/P = Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
1207
ALYW
1207P
AWL
YYWW
1
8
1
8
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Device
Package
Shipping
ORDERING INFORMATION
NCP1207DR2
SOIC-8
2500/Tape & Reel
NCP1207P
PDIP-8
50 Units/Tube
NCP1207DR2G
SOIC-8
(Pb-Free)
2500/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NCP1207
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2
+
+
1
2
3
4
8
7
6
5
Universal Network
+
Figure 1. Typical Application
*Please refer to the application information section
OVP and
Demag
NCP1207
*
V
out
GND
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Function
Description
1
Demag
Core reset detection and OVP
The auxiliary FLYBACK signal ensures discontinuous operation and
offers a fixed overvoltage detection level of 7.2 V.
2
FB
Sets the peak current setpoint
By connecting an Optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand. By bringing this pin
below the internal skip level, device shuts off.
3
CS
Current sense input and
skip cycle level selection
This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the level at which the skip operation takes place.
4
GND
The IC ground
-
5
Drv
Driving pulses
The driver's output to an external MOSFET.
6
V
CC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10
m
F.
7
NC
-
This unconnected pin ensures adequate creepage distance.
8
HV
High-voltage pin
Connected to the high-voltage rail, this pin injects a constant current into
the V
CC
bulk capacitor.
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3
Figure 2. Internal Circuit Architecture
+
-
V
CC
HV
GND
Drv
Demag
-
+
Fault
Mngt.
+
-
7.0
mA
To Internal
Supply
+
12 V, 10 V,
5.3 V (fault)
PON
4.5
m
s
Delay
+
+
5.0 V
OVP
/1.44
8.0
m
s
Blanking
-
+
5.0
m
s
Timeout
Demag
Demag
Overload?
Timeout
Reset
S
R
S*
Q
R*
Q
380 ns
L.E.B.
/3
1.0 V
10 V
50 mV
CS
FB
200
m
A
when Drv
is OFF
Driver: src = 20
sink = 10
*S and R are level triggered whereas S is edge
triggered. R has priority over the other inputs.
V
CC
R
esd
R
int
4.2 V
Soft-Start = 1 ms
MAXIMUM RATINGS
Rating
Symbol
Value
Units
Power Supply Voltage
V
CC
, Drv
16
V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (V
CC
) Pin 5 (Drv) and
Pin 1 (Demag)
-
-0.3 to 10
V
Maximum Current into all pins except V
CC
(6), HV (8) and Demag (1) when 10 V
ESD diodes are activated
-
5.0
mA
Maximum Current in Pin 1
Idem
+3.0/-2.0
mA
Thermal Resistance, Junction-to-Case
R
q
JC
57
C/W
Thermal Resistance, Junction-to-Air, SOIC version
R
q
JA
178
C/W
Thermal Resistance, Junction-to-Air, PDIP version
R
q
JA
100
C/W
Maximum Junction Temperature
TJ
MAX
150
C
Temperature Shutdown
-
155
C
Hysteresis in Shutdown
-
30
C
Storage Temperature Range
-
-60 to +150
C
ESD Capability, HBM Model (All pins except HV)
-
2.0
kV
ESD Capability, Machine Model
-
200
V
Maximum Voltage on Pin 8 (HV), Pin 6 (V
CC
) decoupled to ground with 10
m
F
V
HVMAX
500
V
Minimum Voltage on Pin 8 (HV), Pin 6 (V
CC
) decoupled to ground with 10
m
F
V
HVMIN
40
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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4
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25
C, for min/max values T
J
= 0
C to +125
C, Max T
J
= 150
C,
V
CC
= 11 V unless otherwise noted)
Rating
Pin
Symbol
Min
Typ
Max
Unit
DYNAMIC SELF-SUPPLY
V
CC
Increasing Level at which the Current Source Turns-off
6
VCC
OFF
10.8
12
12.9
V
V
CC
Decreasing Level at which the Current Source Turns-on
6
VCC
ON
9.1
10
10.6
V
V
CC
Decreasing Level at which the Latch-off Phase Ends
6
VCC
latch
-
5.3
-
V
Internal IC Consumption, No Output Load on Pin 5,
F
SW
= 60 kHz
6
I
CC1
-
1.0
1.3
(Note 1)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5,
F
SW
= 60 kHz
6
I
CC2
-
1.6
2.0
(Note 1)
mA
Internal IC Consumption in Latch-off Phase
6
I
CC3
-
330
-
m
A
INTERNAL STARTUP CURRENT SOURCE (T
J
u
0
C)
High-voltage Current Source, V
CC
= 10 V
8
I
C1
4.3
7.0
9.6
mA
High-voltage Current Source, V
CC
= 0
8
I
C2
-
8.0
-
mA
DRIVE OUTPUT
Output Voltage Rise-time @ CL = 1.0 nF, 10-90% of Output
Signal
5
T
r
-
40
-
ns
Output Voltage Fall-time @ CL = 1.0 nF, 10-90% of Output
Signal
5
T
f
-
20
-
ns
Source Resistance
5
R
OH
12
20
36
W
Sink Resistance
5
R
OL
5.0
10
19
W
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3
3
I
IB
-
0.02
-
m
A
Maximum Internal Current Setpoint
3
I
Limit
0.92
1.0
1.12
V
Propagation Delay from Current Detection to Gate OFF State
3
T
DEL
-
100
160
ns
Leading Edge Blanking Duration
3
T
LEB
-
380
-
ns
Internal Current Offset Injected on the CS Pin during OFF Time
3
I
skip
-
200
-
m
A
OVERVOLTAGE SECTION (V
CC
= 11 V)
Sampling Delay after ON Time
1
T
sample
-
4.5
-
m
s
OVP Internal Reference Level
1
V
ref
6.4
7.2
8.0
V
FEEDBACK SECTION (V
CC
= 11 V, Pin 5 Loaded by 1.0 k
W
)
Internal Pull-up Resistor
2
Rup
-
20
-
k
W
Pin 3 to Current Setpoint Division Ratio
-
Iratio
-
3.3
-
-
Internal Soft-start
-
Tss
-
1.0
-
ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (V
pin1
Decreasing)
1
V
TH
35
50
90
mV
Hysteresis (V
pin1
Decreasing)
1
V
H
-
20
-
mV
Input Clamp Voltage
High State (I
pin
1 = 3.0 mA)
Low State (I
pin
1 = -2.0 mA)
1
1
VC
H
VC
L
8.0
-0.9
10
-0.7
12
-0.5
V
V
Demag Propagation Delay
1
T
dem
-
210
-
ns
Internal Input Capacitance at V
pin1
= 1.0 V
1
C
par
-
10
-
pF
Minimum T
OFF
(Internal Blanking Delay after T
ON
)
1
T
blank
-
8.0
-
m
s
Timeout After Last Demag Transition
1
T
out
-
5.0
-
m
s
Pin 1 Internal Impedance
1
R
int
-
28
-
k
W
1. Max value at T
J
= 0
C.
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TYPICAL CHARACTERISTICS
(T
J
= -40
C to 125
C)
TEMPERATURE (
C)
10.4
10.8
11.2
11.6
12.0
12.4
12.8
13.2
-50
-25
0
25
50
75
100
125
VCC
OFF
(V)
Figure 3. V
CC
Increasing Level at which the
Current Source Turns-off versus Temperature
8.8
9.2
9.6
10.0
10.4
10.8
11.2
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
VCC
ON
(V)
Figure 4. V
CC
Decreasing Level at which the
Current Source Turns-on versus Temperature
0.40
0.60
0.80
1.00
1.20
1.40
1.60
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
I
CC1
(mA)
Figure 5. Internal IC Consumption, No Output
Load on Pin 5 versus Temperature
7
1.30
1.50
1.70
1.90
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
I
CC2
(mA)
Figure 6. Internal IC Consumption, Output
Load on Pin 5 versus Temperature
2.10
2.30
1.10
I
C1
(mA)
TEMPERATURE (
C)
Figure 7. Internal Startup Current Source,
V
CC
= 10 V versus Temperature
2
3
4
5
6
7
8
9
10
11
12
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
I
limit
(V)
Figure 8. Maximum Internal Current Setpoint
versus Temperature
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-50
-25
0
25
50
75
100
125
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6
TYPICAL CHARACTERISTICS
(T
J
= -40
C to 125
C)
-50
-25
0
25
50
75
100
125
5
10
15
20
25
30
35
40
TEMPERATURE (
C)
R
OH
(
W
)
Figure 9. Source Resistance versus
Temperature
0
0
2
4
6
8
10
12
14
16
18
20
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
R
OL
(
W
)
Figure 10. Sink Resistance versus
Temperature
TEMPERATURE (
C)
V
TH
(mV)
Figure 11. Input Voltage (V
pin1
Decreasing)
versus Temperature
TEMPERATURE (
C)
V
ref
(V)
Figure 12. OVP Internal Reference Level
versus Temperature
0
20
40
60
80
100
120
-50
-25
0
25
50
75
100
125
6.0
6.5
7.0
7.5
8.0
-50
-25
0
25
50
75
100
125
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TYPICAL CHARACTERISTICS
(T
J
= -50
C to 125
C)
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
-50
-25
0
25
50
75
100
125
Figure 13. Minimum T
off
versus Temperature
Figure 14. Internal Soft-start versus
Temperature
TEMPERATURE (
C)
TEMPERATURE (
C)
6.5
7.0
7.5
8.0
9.5
10
T
of
f
(
m
s)
T
ss
(ms)
8.5
9.0
-50
-25
0
25
50
75
100
125
TEMPERATURE (
C)
Figure 15. DMG Pin Internal Resistance versus
Temperature
R
int
(k
W
)
0
10
20
30
40
50
-50
-25
0
25
50
75
100
125
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8
Application Information
Introduction
The NCP1207 implements a standard current mode
architecture where the switch-off time is dictated by the
peak current setpoint whereas the core reset detection
triggers the turn-on event. This component represents the
ideal candidate where low part-count is the key parameter,
particularly in low-cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Thanks to its
high-performance
High-Voltage technology, the NCP1207
incorporates all the necessary components / features needed
to build a rugged and reliable Switch-Mode Power Supply
(SMPS):
Transformer core reset detection: borderline / critical
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn-on losses and no secondary diode recovery losses.
The converter also stays a first-order system and
accordingly eases the feedback loop design.
Quasi-resonant operation: by delaying the turn-on
event, it is possible to re-start the MOSFET in the
minimum of the drain-source wave, ensuring reduced
EMI / video noise perturbations. In nominal power
conditions, the NCP1207 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode.
Dynamic Self-Supply (DSS): due to its Very High
Voltage Integrated Circuit (VHVIC) technology,
ON Semiconductor's NCP1207 allows for a direct pin
connection to the high-voltage DC rail. A dynamic
current source charges up a capacitor and thus provides
a fully independent V
CC
level to the NCP1207. As a
result, there is no need for an auxiliary winding whose
management is always a problem in variable output
voltage designs (e.g. battery chargers).
Overvoltage Protection (OVP): by sampling the plateau
voltage on the demagnetization winding, the NCP1207
goes into latched fault condition whenever an
overvoltage condition is detected. The controller stays
fully latched in this position until the V
CC
is cycled
down 4.0 V, e.g. when the user un-plugs the power
supply from the mains outlet and re-plugs it.
External latch trip point: by externally forcing a level
on the OVP greater than the internal setpoint, it is
possible to latch-off the IC, e.g. with a signal coming
from a temperature sensor.
Adjustable skip cycle level: by offering the ability to
tailor the level at which the skip cycle takes place, the
designer can make sure that the skip operation only
occurs at low peak current. This point guarantees a
noise-free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load
conditions.
Overcurrent Protection (OCP): by continuously
monitoring the FB line activity, NCP1207 enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power operation
which prevents from any lethal thermal runaway. As
soon as the default disappears, the power supply
resumes operation. Unlike other controllers, overload
detection is performed independently of any auxiliary
winding level. In presence of a bad coupling between
both power and auxiliary windings, the short circuit
detection can be severely affected. The DSS naturally
shields you against these troubles.
Dynamic Self-Supply
The DSS principle is based on the charge/discharge of the
V
CC
bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with some
simple logical equations:
POWER-ON: IF V
CC
< VCC
OFF
THEN Current Source
is ON, no output pulses
IF V
CC
decreasing > VCC
ON
THEN Current Source is
OFF, output is pulsing
IF V
CC
increasing < VCC
OFF
THEN Current Source is
ON, output is pulsing
Typical values are: VCC
OFF
= 12 V, VCC
ON
= 10 V
To better understand the operational principle, Figure 16's
sketch offers the necessary light.
Figure 16. The Charge/Discharge Cycle Over a 10
m
F
V
CC
Capacitor
V
CC
CURRENT
SOURCE
V
RIPPLE
= 2 V
ON
OFF
VCC
OFF
= 12 V
VCC
ON
= 10 V
Output Pulses
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The DSS behavior actually depends on the internal IC
consumption and the MOSFET's gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
Fsw
Qg
V
CC
with:
Fsw = maximum switching frequency
Qg = MOSFET's gate charge
V
CC
= V
GS
level applied to the gate
To obtain the output current, simply divide this result by
V
CC
: I
driver
= F
SW
Qg = 1.6 mA. The total standby power
consumption at no-load will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver's efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1207 consumption
(neglecting the switching losses of the HV current source).
If I
CC2
equals 2.3 mA @ T
J
= 60
C, then the power
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
805 mW. For design and reliability reasons, it would be
interested to reduce this source of wasted power that
increase the die temperature. This can be achieved by using
different methods:
1. Use a MOSFET with lower gate charge Qg.
2. Connect pin 8 through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes
VmainsPEAK
@
2
p
. Our power contribution
example drops to: 223 V x 2.3 mA = 512 mW. If a
resistor is installed between the mains and the diode,
you further force the dissipation to migrate from the
package to the resistor. The resistor value should
account for low-line startups.
1
2
3
4
8
7
6
5
HV
1N4007
MAINS
6
5
1
2
Figure 17. A simple diode naturally reduces the
average voltage on pin 8
C
bulk
When using Figure 17 option, it is important to check
the absence of any negative ringing that could occur
on pin 8. The resistor in series should help to damp
any parasitic LC network that would ring when
suddenly applying the power to the IC. Also, since
the power disappears during 10 ms (half-wave
rectification), CV
CC
should be calculated to supply
the IC during these holes in the supply
3. Permanently force the V
CC
level above V
CCH
with
an auxiliary winding. It will automatically
disconnect
the internal startup source and the IC will
be fully self-supplied from this winding. Again, the
total power drawn from the mains will significantly
decrease. Make sure the auxiliary voltage never
exceeds the 16 V limit.
Skipping Cycle Mode
The NCP1207 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so-called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18) and
follows the following formula:
1
2
@
Lp
@
Ip
2
@
Fsw
@
Dburst
with:
Lp = primary inductance
Fsw = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D
burst
= burst width / burst recurrence
Figure 18. The skip cycle takes place at low peak
currents which guaranties noise free operation
0
300
200
100
MAX PEAK
CURRENT
WIDTH
RECURRENCE
SKIP CYCLE
CURRENT LIMIT
NORMAL CURRENT
MODE OPERATION
CURRENT SENSE SIGNAL (mV)
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10
Figure 19. A patented method allows for skip level
selection via a series resistor inserted in series
with the current
+
-
RESET
DRIVER
R
sense
R
skip
+
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200
m
A
2
3
The skip level selection is done through a simple resistor
inserted between the current sense input and the sense element.
Every time the NCP1207 output driver goes low, a 200
mA
source forces a current to flow through the sense pin
(Figure 19): when the driver is high, the current source is off
and the current sense information is normally processed. As
soon as the driver goes low, the current source delivers 200
mA
and develops a ground referenced voltage across R
skip
. If this
voltage is below the feedback voltage, the current sense
comparator stays in the high state and the internal latch can be
triggered by the next clock cycle. Now, if because of a low load
mode the feedback voltage is below R
skip
level, then the
current sense comparator permanently resets the latch and the
next clock cycle (given by the demagnetization detection) is
ignored: we are skipping cycles as shown by Figure 20. As
soon as the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1207. To the opposite, in low output power conditions, no
more ringing waves are present on the drain and the toggling
of the current sense comparator together with the internal 5
ms
timeout initiates a new cycle start. In normal operating
conditions, e.g. when the drain oscillations are generous, the
demagnetization comparator can detect the 50 mV crossing
and gives the "green light", alone, to re-active the power
switch. However, when skip cycle takes place (e.g. at low
output power demands), the re-start event slides along the
drain ringing waveforms (actually the valley locations) which
decays more or less quickly, depending on the
L
primary
-C
parasitic
network damping factor. The situation can
thus quickly occur where the ringing becomes too weak to be
detected by the demagnetization comparator: it then
permanently stays locked in a given position and can no longer
deliver the "green light" to the controller. To help in this
situation, the NCP1207 implements a 5
ms timeout generator:
each time the 50 mV crossing occurs, the timeout is reset. So,
as long as the ringing becomes too low, the timeout generator
starts to count and after 5
ms, it delivers its "green light". If the
skip signal is already present then the controller re-starts;
otherwise the logic waits for it to set the drive output high.
Figure 20 depicts these two different situations:
Demag Re-start
Current Sense and Timeout Re-start
5
m
s
5
m
s
Drain
Signal
Timeout
Signal
Drain
Signal
Timeout
Signal
Figure 20. When the primary natural ringing becomes too low, the internal timeout together with the sense
comparator initiates a new cycle when FB passes the skip level.
NCP1207
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11
Demagnetization Detection
The core reset detection is done by monitoring the voltage
activity on the auxiliary winding. This voltage features a
FLYBACK polarity. The typical detection level is fixed at
50 mV as exemplified by Figure 21.
POSSIBLE
RE-STARTS
50 mV
Figure 21. Core reset detection is done through a
dedicated auxiliary winding monitoring
7.0
5.0
3.0
1.0
-1.0
0 V
DEMAG SIGNAL (V)
Figure 22. Internal Pad Implementation
TO INTERNAL
COMPARATOR
Aux
R
esd
R
dem
ESD2
ESD1
4
5
2
4
1
R
esd
+ R
int
= 28 k
R
int
3
1
An internal timer prevents any re-start within 8.0
ms
further to the driver going-low transition. This prevents the
switching frequency to exceed (1 / (T
ON
+ 8.0
ms)) but also
avoid false leakage inductance tripping at turn-off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The 1207 demagnetization detection pad features a
specific component arrangement as detailed by Figure 22. In
this picture, the zener diodes network protect the IC against
any potential ESD discharge that could appear on the pins.
The first ESD diode connected to the pad, exhibits a parasitic
capacitance. When this parasitic capacitance (10 pF
typically) is combined with R
dem
, a re-start delay is created
and the possibility to switch right in the drain-source wave
exists. This guarantees QR operation with all the associated
benefits (low EMI, no turn-on losses etc.). R
dem
should be
calculated to limit the maximum current flowing through
pin 1 to less than +3 mA/-2 mA. If during turn-on, the
auxiliary winding delivers 30 V (at the highest line level),
then the minimum R
dem
value is defined by:
(30 V + 0.7 V) / 2 mA = 14.6 k
W.
This value will be further increased to introduce a re-start
delay and also a slight filtering in case of high leakage
energy.
Figure 23 portrays a typical V
DS
shot at nominal output
power.
Figure 23. The NCP1207 Operates in
Borderline / Critical Operation
400
300
200
100
0
DRAIN VOL
T
AGE (V)
Overvoltage Protection
The overvoltage protection works by sampling the plateau
voltage 4.5
ms after the turn-off sequence. This delay
guarantees a clean plateau, providing that the leakage
inductance ringing has been fully damped. If this would not
be the case, the designer should install a small RC damper
across the transformer primary inductance connections.
Figure 24 shows where the sampling occurs on the auxiliary
winding.
Figure 24. A voltage sample is taken 4.5
m
s after
the turn-off sequence
8.0
6.0
4.0
2.0
0
SAMPLING HERE
DEMAG SIGNAL (V)
4.5
m
s
When an OVP condition has been detected, the NCP1207
enters a latch-off phase and stops all switching operations.
The controller stays fully latched in this position and the
DSS is still active, keeping the V
CC
between 5.3 V/12 V as
in normal operations. This state lasts until the V
CC
is cycled
down 4 V, e.g. when the user unplugs the power supply from
the mains outlet.
By default, the OVP comparator is biased to a 5 V
reference level and pin 1 is routed via a divide by 1.44
network. As a result, when V
pin1
reaches 7.2 V, the OVP
comparator is triggered. The threshold can thus be adjusted
by either modifying the power winding to auxiliary winding
turn ratios to match this 7.2 V level, or insert a resistor from
pin1 to ground to cope with your design requirement.
NCP1207
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12
Latching Off the NCP1207
In certain cases, it can be very convenient to externally
shut down permanently the NCP1207 via a dedicated signal,
e.g. coming from a temperature sensor. The reset occurs
when the user unplugs the power supply from the mains
outlet. To trigger the latch-off, a CTN (Figure 25) or a
simple NPN transistor (Figure 26) can do the work.
Figure 25. A simple CTN triggers the latch-off as
soon as the temperature exceeds a given setpoint
1
2
3
4
8
7
6
5
CTN
Aux
NCP1207
ON/OFF
Figure 26. A simple transistor arrangement allows
to trigger the latch-off by an external signal
1
2
3
4
8
7
6
5
NCP1207
Aux
Shutting Off the NCP1207
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 27. When OFF,
Q1 is transparent to the operation. When forward biased, the
transistor pulls the FB pin to ground (V
CE(sat)
200 mV) and
permanently disables the IC. A small time constant on the
transistor base will avoid false triggering (Figure 27).
Figure 27. A simple bipolar transistor totally
disables the IC
1
2
3
4
8
7
6
5
NCP1207
10 nF
Q1
10 k
ON/OFF
1
2
3
Power Dissipation
The NCP1207 is directly supplied from the DC rail
through the internal DSS circuitry. The DSS being an
auto-adaptive circuit (e.g. the ON/OFF duty-cycle adjusts
itself depending on the current demand), the current flowing
through the DSS is therefore the direct image of the
NCP1207 current consumption. The total power dissipation
can be evaluated using:
(VHVDC
*
11 V)
@
ICC2
. If we
operate the device on a 250 Vac rail, the maximum rectified
voltage can go up to 350 Vdc. As a result, the worse case
dissipation occurs at the maximum switching frequency and
the highest line. The dissipation is actually given by the
internal consumption of the NCP1207 when driving the
selected MOSFET. The best method to evaluate this total
consumption is probably to run the final circuit from a
50 Vdc source applied to pin 8 and measure the average
current flowing into this pin. Suppose that we find 2.0 mA,
meaning that the DSS duty-cycle will be 2.0/7.0 = 28.6%.
From the 350 Vdc rail, the part will dissipate:
350 V
@
2.0 mA
+
700 mW
(however this 2.0 mA number
will drop at higher operating junction temperatures).
A DIP8 package offers a junction-to-ambient thermal
resistance R
qJA
of 100
C/W. The maximum power
dissipation can thus be computed knowing the maximum
operating ambient temperature (e.g. 70
C) together with
the maximum allowable junction temperature (125
C):
P max
+
TJmax
*
TAmax
R
q
JA
t
550 mW
. As we can see, we
do not reach the worse consumption budget imposed by the
operating conditions. Several solutions exist to cure this
trouble:
The first one consists in adding some copper area around
the NCP1207 DIP8 footprint. By adding a min pad area
of 80 mm
2
of 35
mm copper (1 oz.) R
qJA
drops to about
75
C/W. Maximum power then grows up to 730 mW.
A resistor Rdrop needs to be inserted with pin 8 to
a) avoid negative spikes at turn-off (see below)
b) split the power budget between this resistor and the
package. The resistor is calculated by leaving at least 50 V
on pin 8 at minimum input voltage (suppose 100 Vdc in
our case):
Rdrop
v
Vbulkmin
*
50 V
7.0 mA
t
7.1 k
W
. The
power dissipated by the resistor is thus:
Pdrop
+
VdropRMS
2
Rdrop
+
IDSS
@
Rdrop
@
DSSduty
*
cycle
2
Rdrop
+
7.0 mA
@
7.1 k
W @
0.286
2
7.1 k
W
+
99.5 mW
Please refer to the application note AND8069 available
from www.onsemi.com/pub/ncp1200.
NCP1207
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13
If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary
winding and the V
CC
pin which will disable the DSS
operation (V
CC
u 10 V).
The SOIC package offers a 178
C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decrease this number: 12 mm
12 mm to drop
R
qJA
down to 100
C/W with 35
mm copper thickness (1 oz.)
or 6.5 mm
6.5 mm with 70 mm copper thickness (2 oz.).
As one can see, we do not recommend using the SO-8
package and the DSS if the part operates at high switching
frequencies. In that case, an auxiliary winding is the best
solution.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short-circuit protection. A
short-circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation, NCP1207
hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
manner with a low duty-cycle. The system recovers when
the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time-out used by this IC
works with the V
CC
decoupling capacitor: as soon as the
V
CC
decreases from the VCC
OFF
level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC
ON
level is
reached, the controller stops the driving pulses, prevents the
self-supply current source to restart and puts all the circuitry
in standby, consuming as little as 330
mA typical (I
CC3
parameter). As a result, the V
CC
level slowly discharges
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: V
CC
rises toward 12 V and again delivers output
pulses at the VCC
OFF
crossing point. If the fault condition
has been removed before VCC
ON
approaches, then the IC
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 28 shows the evolution of the signals in
presence of a fault.
If the fault is relaxed during the V
CC
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when V
CC
reached VCC
ON
, then the controller
cuts everything off until recovery.
Figure 28.
TIME
TIME
TIME
INTERNAL
FAULT FLAG
V
CC
12 V
10 V
5.3 V
DRV
DRIVER
PULSES
FAULT IS
RELAXED
FAULT OCCURS HERE
STARTUP PHASE
REGULATION
OCCURS HERE
LATCH-OFF
PHASE
Soft-Start
The NCP1207 features an internal 1 ms soft-start to soften
the constraints occurring in the power supply during startup.
It is activated during the power on sequence. As soon as V
CC
reaches VCC
OFF
, the peak current is gradually increased
from nearly zero up to the maximum clamping level (e.g.
1.0
V). The soft-start is also activated during the
overcurrent burst (OCP) sequence. Every restart attempt is
followed by a soft-start activation. Generally speaking, the
soft-start will be activated when V
CC
ramps up either from
zero (fresh power-on sequence) or 5.3 V, the latch-off
voltage occurring during OCP.
NCP1207
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14
Calculating the V
CC
Capacitor
As the above section describes, the fall down sequence
depends upon the V
CC
level: how long does it take for the
V
CC
line to go from 12 V to 10 V? The required time depends
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let's
suppose that this time corresponds to 6.0 ms. Therefore a
V
CC
fall time of 10 ms could be well appropriated in order
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),
we can calculate the required capacitor using the following
formula:
D
t
+ D
V
@
C
i
, with
DV = 2.0 V. Then for a wanted
Dt of 10 ms, C equals 9.0 mF or 22 mF for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330
mA
typical. This happens at V
CC
= 10 V and it remains stuck
until V
CC
reaches 5.3 V: we are in latch-off phase. Again,
using the calculated 22
mF and 330 mA current consumption,
this latch-off phase lasts: 313 ms.
HV Pin Recommended Protection
When the user unplugs a power supply built with a QR
controller such as the NCP1207, two phenomena can
appear:
1. A negative ringing can take place on pin8 due to a
resonance between the primary inductance and
the bulk capacitor. As any CMOS device, the
NCP1207 is sensitive to negative voltages that
could appear on it's pins and could create an
internal latch-up condition.
2. When the bulk capacitor discharges, the internal
latch is reset by the voltage developed over the
sense resistor and the ON time expands as less
voltage is available. When the high-voltage rail
becomes too low, the gate drives permanently
stays high since no reset occurs. This situation is
not desirable in many applications.
For the above reasons, we strongly recommend to add a
high-voltage diode like a 1N4007 between the bulk
capacitor and the V
CC
pin. When the bulk level collapses, it
naturally shuts the controller down and eradicates the two
above problems.
Figure 29.
D1
1N4007
8
7
6
5
1
2
3
4
Cbulk
+
NCP1207
+
HV
Operation Shots
Below are some oscilloscope shots captured at
V
in
= 120 VDC with a transformer featuring a 800
mH
primary inductance.
Figure 30.
This plot gathers waveforms captured at three different
operating points:
1
st
upper plot: free run, valley switching operation,
P
out
= 26 W
2
nd
middle plot: min T
off
clamps the switching frequency
and selects the second valley
3
rd
lowest plot: the skip slices the second valley pattern
and will further expand the burst as P
out
goes low
NCP1207
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15
Figure 31.
V
GATE
(5 V/div)
V
Rsense
(200 mV/div)
200
m
A X R
SKIP
Current Sense Pin (200 mV/div)
This picture explains how the 200
mA internal offset
current creates the skip cycle level.
Figure 32.
V
CC
(5 V/div)
V
GATE
(5 V/div)
The short-circuit protection forces the IC to enter burst in
presence of a secondary overload.
NCP1207
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16
PACKAGE DIMENSIONS
PDIP-8
N SUFFIX
CASE 626-05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
5
8
F
NOTE 2
-A-
-B-
-T-
SEATING
PLANE
H
J
G
D
K
N
C
L
M
M
A
M
0.13 (0.005)
B
M
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.40
10.16
0.370
0.400
B
6.10
6.60
0.240
0.260
C
3.94
4.45
0.155
0.175
D
0.38
0.51
0.015
0.020
F
1.02
1.78
0.040
0.070
G
2.54 BSC
0.100 BSC
H
0.76
1.27
0.030
0.050
J
0.20
0.30
0.008
0.012
K
2.92
3.43
0.115
0.135
L
7.62 BSC
0.300 BSC
M
---
10
---
10
N
0.76
1.01
0.030
0.040
_
_
NCP1207
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17
PACKAGE DIMENSIONS
SOIC-8
D1, D2 SUFFIX
CASE 751-07
ISSUE AB
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
NCP1207
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18
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NCP1207/D
The product described herein (NCP1207), may be covered by one or more of the following U.S. patents: 6,362,067, 6,385,060, 6,385,061, 6,429,709,
6,587,357, 6,633,193. There may be other patents pending.
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