Document Outline

COVER
INTRODUCTION
CHAPTER 1 GENERAL
- 1.1 FUNCTION LIST
- 1.2 ORDERING INFORMATION
- 1.3 BLOCK DIAGRAM
- 1.4 PIN CONFIGURATION (Top View)
CHAPTER 2 PIN FUNCTIONS
- 2.1 PIN FUNCTIONS
  - 2.1.1 Pins in Normal Operation Mode
  - 2.1.2 Pins in Program Memory Write/Verify Mode ... uPD17P132, 17P133 only
- 2.2 PIN INPUT/OUTPUT CIRCUIT
- 2.3 HANDLING UNUSED PINS
- 2.4 CAUTIONS ON USE OF THE RESET# AND INT PINS (in Normal Operation Mode only)
CHAPTER 3 PROGRAM COUNTER (PC)
- 3.1 PROGRAM COUNTER CONFIGURATION
- 3.2 PROGRAM COUNTER OPERATION
  - 3.2.1 Program Counter at Reset
  - 3.2.2 Program Counter during Execution of the Branch Instruction (BR)
  - 3.2.3 Program Counter during Execution of Subroutine Calls (CALL)
  - 3.2.4 Program Counter during Execution of Return Instructions (RET, RETSK, RETI)
  - 3.2.5 Program Counter during Table Reference (MOVT)
  - 3.2.6 Program Counter during Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT SKF)
  - 3.2.7 Program Counter When an Interrupt Is Received
- 3.3 CAUTIONS ON PROGRAM COUNTER OPERATION
CHAPTER 4 PROGRAM MEMORY (ROM)
- 4.1 PROGRAM MEMORY CONFIGURATION
- 4.2 PROGRAM MEMORY USAGE
  - 4.2.1 Flow of the Program
  - 4.2.2 Table Reference
CHAPTER 5 DATA MEMORY (RAM)
- 5.1 DATA MEMORY CONFIGURATION
  - 5.1.1 System Register (SYSREG)
  - 5.1.2 Data Buffer (DBF)
  - 5.1.3 General Register (GR)
  - 5.1.4 Port Registers
  - 5.1.5 General Data Memory
  - 5.1.6 Uninstalled Data Memory
CHAPTER 6 STACK
- 6.1 STACK CONFIGURATION
- 6.2 FUNCTIONS OF THE STACK
- 6.3 ADDRESS STACK REGISTER
- 6.4 INTERRUPT STACK REGISTER
- 6.5 STACK POINTER (SP) AND INTERRUPT STACK REGISTER
- 6.6 STACK OPERATION DURING SUBROUTINES, TABLE REFERENCES, AND INTERRUPTS
  - 6.6.1 Stack Operation during Subroutine Calls (CALL) and Returns (RET, RETSK)
  - 6.6.2 Stack Operation during Table Reference (MOVT DBF, @AR)
  - 6.6.3 Executing RETI Instruction
- 6.7 STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS
CHAPTER 7 SYSTEM REGISTER (SYSREG)
- 7.1 SYSTEM REGISTER CONFIGURATION
- 7.2 ADDRESS REGISTER (AR)
  - 7.2.1 Address Register Configuration
  - 7.2.2 Address Register Functions
- 7.3 WINDOW REGISTER (WR)
  - 7.3.1 Window Register Configuration
  - 7.3.2 Window Register Functions
- 7.4 BANK REGISTER (BANK)
- 7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (Memory Pointer: MP)
  - 7.5.1 Index Register (IX)
  - 7.5.2 Data Memory Row Address Pointer (Memory Pointer: MP)
  - 7.5.3 MPE=0 and IXE=0 (No Data Memory Modification)
  - 7.5.4 MPE=1 and IXE=0 (Diagonal Indirect Data Transfer)
  - 7.5.5 MPE=0 and IXE=1 (Index Modification)
- 7.6 GENERAL REGISTER POINTER (RP)
  - 7.6.1 General Register Pointer Configuration
  - 7.6.2 Functions of the General Register Pointer
- 7.7 PROGRAM STATUS WORD (PSWORD)
  - 7.7.1 Program Status Word Configuration
  - 7.7.2 Functions of the Program Status Word
  - 7.7.3 Index Enable Flag (IXE)
  - 7.7.4 Zero Flag (Z) and Compare Flag (CMP)
  - 7.7.5 Carry Flag (CY)
  - 7.7.6 Binary-Coded Decimal Flag (BCD)
  - 7.7.7 Caution on Use of Arithmetic Operations on the Program Status Word
- 7.8 CAUTIONS ON USE OF THE SYSTEM REGISTER
  - 7.8.1 Reserved Words for Use with the System Register
  - 7.8.2 Handling of System Register Addresses Fixed at 0
CHAPTER 8 GENERAL REGISTER (GR)
- 8.1 GENERAL REGISTER CONFIGURATION
- 8.2 FUNCTIONS OF THE GENERAL REGISTER
CHAPTER 9 REGISTER FILE (RF)
- 9.1 REGISTER FILE CONFIGURATION
  - 9.1.1 Configuration of the Register File
  - 9.1.2 Relationship between the Register File and Data Memory
- 9.2 FUNCTIONS OF THE REGISTER FILE
  - 9.2.1 Functions of the Register File
  - 9.2.2 Control Register Functions
  - 9.2.3 Register File Manipulation Instructions
- 9.3 CONTROL REGISTER
- 9.4 CAUTIONS ON USING THE REGISTER FILE
  - 9.4.1 Concerning Operation of the Control Register (Read-Only and Unused Registers)
  - 9.4.2 Register File Symbol Definitions and Reserved Words
CHAPTER 10 DATA BUFFER (DBF)
- 10.1 DATA BUFFER CONFIGURATION
- 10.2 FUNCTIONS OF THE DATA BUFFER
  - 10.2.1 Data Buffer and Peripheral Hardware
  - 10.2.2 Data Transfer with Peripheral Hardware
  - 10.2.3 Table Reference
CHAPTER 11 ARITHMETIC AND LOGIC UNIT
- 11.1 ALU BLOCK CONFIGURATION
- 11.2 FUNCTIONS OF THE ALU BLOCK
  - 11.2.1 Functions of the ALU
  - 11.2.2 Functions of Temporary Registers A and B
  - 11.2.3 Functions of the Status Flip-flop
  - 11.2.4 Performing Operations in 4-Bit Binary
  - 11.2.5 Performing Operations in BCD
  - 11.2.6 Performing Operations in the ALU Block
- 11.3 ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD)
  - 11.3.1 Addition and Subtraction When CMP=0 and BCD=0
  - 11.3.2 Addition and Subtraction When CMP=1 and BCD=0
  - 11.3.3 Addition and Subtraction When CMP=0 and BCD=1
  - 11.3.4 Addition and Subtraction When CMP=1 and BCD=1
  - 11.3.5 Cautions on Use of Arithmetic Operations
- 11.4 LOGICAL OPERATIONS
- 11.5 BIT JUDGEMENT
  - 11.5.1 TRUE (1) Bit Judgement
  - 11.5.2 FALSE (0) Bit Judgement
- 11.6 COMPARISON JUDGEMENT
  - 11.6.1 "Equal to" Judgement
  - 11.6.2 "Not Equal to" Judgement
  - 11.6.3 "Greater Than or Equal to" Judgement
  - 11.6.4 "Less Than" Judgement
- 11.7 ROTATIONS
  - 11.7.1 Rotation to the Right
  - 11.7.2 Rotation to the Left
CHAPTER 12 PORTS
- 12.1 PORT 0A (P0A0, P0A1, P0A2, P0A3)
- 12.2 PORT 0B (P0B0, P0B1, P0B2, P0B3)
- 12.3 PORT 0C (P0C0, P0C1, P0C2, P0C3) ... in the case of the uPD17120 and 17121
- 12.4 PORT 0C (P0C0/Cin0, P0C1/Cin1, P0C2/Cin2, P0C3/Cin3) ... in the case of the uPD17132, 17133, 17P132, and 17P133
- 12.5 PORT 0D (P0D0/SCK#, P0D1/SO, P0D2/SI, P0D3/TMOUT#)
- 12.6 PORT 0E (P0E0, P0E1/Vref) ... Vref; uPD17132, 17133, 17P132, and 17P133 only
  - 12.6.1 Cautions when Operating Port Registers
- 12.7 PORT CONTROL REGISTER
  - 12.7.1 Input/Output Switching by Group I/O
  - 12.7.2 Input/Output Switching by Bit I/O
CHAPTER 13 PERIPHERAL HARDWARE
- 13.1 8-BIT TIMER COUNTER (TM)
  - 13.1.1 8-Bit Timer Counter Configuration
  - 13.1.2 8-bit Timer Counter Control Register
  - 13.1.3 Operation of 8-bit Timer Counters
  - 13.1.4 Selecting Count Pulse
  - 13.1.5 Setting a Count Value in Modulo Register and Calculation Method
  - 13.1.6 Margin of Error of Interval Time
  - 13.1.7 Reading Count Register Values
  - 13.1.8 Timer Output
  - 13.1.9 Timer Resolution and Maximum Setting Time
- 13.2 COMPARATOR (uPD17132, 17133, 17P132, AND 17P133 ONLY)
  - 13.2.1 Configuration of Comparator
  - 13.2.2 Functions of Comparator
- 13.3 SERIAL INTERFACE (SIO)
  - 13.3.1 Functions of the Serial Interface
  - 13.3.2 3-wire Serial Interface Operation Modes
  - 13.3.3 Setting Values in the Shift Register
  - 13.3.4 Reading Values from the Shift Register
  - 13.3.5 Program Example of Serial Interface
CHAPTER 14 INTERRUPT FUNCTIONS
- 14.1 INTERRUPT SOURCES AND VECTOR ADDRESS
- 14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT
  - 14.2.1 Interrupt Request Flag (IRQxxx) and the Interrupt Enable Flag (IPxxx)
  - 14.2.2 EI/DI Instruction
- 14.3 INTERRUPT SEQUENCE
  - 14.3.1 Acceptance of Interrupts
  - 14.3.2 Return from the Interrupt Routine
  - 14.3.3 Interrupt Acceptance Timing
- 14.4 PROGRAM EXAMPLE OF INTERRUPT
CHAPTER 15 STANDBY FUNCTIONS
- 15.1 OUTLINE OF STANDBY FUNCTION
- 15.2 HALT MODE
  - 15.2.1 HALT Mode Setting
  - 15.2.2 Start Address after HALT Mode is Canceled
  - 15.2.3 HALT Setting Condition
- 15.3 STOP MODE
  - 15.3.1 STOP Mode Setting
  - 15.3.2 Start Address after STOP Mode Cancellation
  - 15.3.3 STOP Setting Condition
CHAPTER 16 RESET
- 16.1 RESET FUNCTIONS
- 16.2 RESETTING
- 16.3 POWER-ON/POWER-DOWN RESET FUNCTION
  - 16.3.1 Conditions Required to Enable the Power-On Reset Function
  - 16.3.2 Description and Operation of the Power-On Reset Function
  - 16.3.3 Condition Required for Use of the Power-Down Reset Function
  - 16.3.4 Description and Operation of the Power-Down Reset Function
CHAPTER 17 ONE-TIME PROM WRITING/VERIFYING
- 17.1 DIFFERENCES BETWEEN MASK ROM VERSION AND ONE-TIME PROM VERSION
- 17.2 OPERATING MODE IN PROGRAM MEMORY WRITING/VERIFYING
- 17.3 WRITING PROCEDURE OF PROGRAM MEMORY
- 17.4 READING PROCEDURE OF PROGRAM MEMORY
CHAPTER 18 INSTRUCTION SET
- 18.1 OVERVIEW OF THE INSTRUCTION SET
- 18.2 LEGEND
- 18.3 LIST OF THE INSTRUCTION SET
- 18.4 ASSEMBLER (AS17K) MACRO INSTRUCTIONS
- 18.5 INSTRUCTIONS
  - 18.5.1 Addition Instructions
  - 18.5.2 Subtraction Instructions
  - 18.5.3 Logical Operation Instructions
  - 18.5.4 Judgment Instruction
  - 18.5.5 Comparison Instructions
  - 18.5.6 Rotation Instructions
  - 18.5.7 Transfer Instructions
  - 18.5.8 Branch Instructions
  - 18.5.9 Subroutine Instructions
  - 18.5.10 Interrupt Instructions
  - 18.5.11 Other Instructions
CHAPTER 19 ASSEMBLER RESERVED WORDS
- 19.1 MASK OPTION PSEUDO INSTRUCTIONS
  - 19.1.1 OPTION and ENDOP Pseudo Instructions
  - 19.1.2 Mask Option Definition Pseudo Instructions
- 19.2 RESERVED SYMBOLS
  - 19.2.1 List of Reserved Symbols (uPD17120, 17121)
  - 19.2.2 List of Reserved Symbols (uPD17132, 17133, 17P132, 17P133)
APPENDIX A DEVELOPMENT TOOLS
APPENDIX B ORDERING MASK ROM
APPENDIX C CAUTIONS TO TAKE IN SYSTEM CLOCK OSCILLATION CIRCUIT CONFIGURATIONS
APPENDIX D INSTRUCTION LIST

Document No. IEU-1367A
(O. D. No. IEU-835A)
Date Published July 1995 P
Printed in Japan

PD17120

PD17121

PD17132

PD17133

PD17P132

PD17P133

PD17120 SUBSERIES

4-BIT SINGLE-CHIP MICROCONTROLLER

1993

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide

and ultimately degrade the device operation. Steps must be taken to stop generation of static

electricity as much as possible, and quickly dissipate it once, when it has occurred. Environ-

mental control must be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor devices must be

stored and transported in an anti-static container, static shielding bag or conductive material.

All test and measurement tools including work bench and floor should be grounded. The

operator should be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is

provided to the input pins, it is possible that an internal input level may be generated due to

noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS

devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused pins must be

judged device by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source

is turned ON, the devices with reset function have not yet been initialized. Hence, power-on

does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immediately after power-

on for devices having reset function.

SIMPLEHOST is a trademark of NEC Corporation.

MS-DOS

and WINDOWS

are trademarks of Microsoft Corporation.

PC/AT and PC DOS are trademarks of IBM Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be

prohibited without governmental license, the need for which must be judged by the customer. The export or re-
export of this product from a country other than Japan may also be prohibited without a license from that country.

Please call an NEC sales representative.

The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M7 94.11

INTRODUCTION

Targeted Reader

This manual is intended for the user engineers who understand functions of the

PD17120 subseries and design their application systems using the

PD17120 sub-

series

Purpose

The purpose of this manual is for the user to understand the hardware functions of

the

PD17120 subseries.

Use

The manual assumes that the reader has a general knowledge of electricity, logic

circuits, microcontrollers.

· To understand the functions of the

PD17120 subseries in a general way;

Read the manual from CHAPTER 1.

· To look up instruction functions in detail when you know the mnemonic of

an instruction;

Use APPENDIX D INSTRUCTION LIST.

· To look up an instruction when you do not know its mnemonic but know

outlines of the function;

Refer to 18.3 LIST OF THE INSTRUCTION SET for search for the mnemonic

of the instruction, then see 18.5 INSTRUCTIONS for the function.

· To look up electrical characteristics of the

PD17120 subseries;

Refer to DATA SHEET.

Legend

Data representation weight

: High-order and low-order digits are indicated from

left to right.

Active low representation

ЧЧЧ

(pin or signal name is overlined)

Address of memory map

: Top: low, Bottom: high

Note

: Explanation of Note in the text

Caution

: Caution to which you should pay attention

Remark

: Supplementary explanation to the text

Number representation

: Binary number

...

ЧЧЧЧ

Decimal number

...

ЧЧЧЧ

Hexadecimal number ...

ЧЧЧЧ

EEU-847 [EEU-1412]

EEU-603 [EEU-1287]

EEU-907 [EEU-1464]

Relevant Documents The following documents are provided for the

PD17120 subseries.

The numbers listed in the table are the document numbers.

Some related documents are preliminary versions. This document, however, is not

indicated as "Preliminary".

Part Number

PD17120

PD17121

PD17132

PD17133

PD17P132

PD17P133

Document Name

Data sheet

IC-8407

IC-8399

IC-8412

IC-8411

ID-8419

ID-8426

[IC-2972]

[IC-2976]

[IC-2973]

[IC-2974]

[ID-2971]

[ID-2983]

User's manual

This manual [IEU-1367]

IE-17K

CLICE Ver.1.6

EEU-929 [EEU-1467]

User's manual

IE-17K-ET

CLICE-ET Ver.1.6

EEU-931 [EEU-1466]

User's manual

SE board

User's manual

SIMPLEHOST

EEU-723 [EEU-1336] (Introduction)

User's manual

EEU-724 [EEU-1337] (Reference)

AS17K (Ver.1.11)

User's manual

Device file

User's manual

Remark

The numbers inside [ ] indicate English document number.

The

PD17120 subseries has different pin names and signal names depending on the system clock type, as

shown in the table below.

System Clock

RC Oscillation

Ceramic Oscillation

PD17120

PD17121

PD17132

PD17133

Pin/Signal Names

PD17P132

PD17P133

OSC

OUT

System Clock Frequency

Unless otherwise specified, this manual uses X

, X

OUT

, and f

for descriptions. When using the

PD17120,

17132, and 17P132, please change the readings to OSC

, OSC

and f

System Clock

Oscillation Pin

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Datasheet: D17133CS (NEC)

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