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copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
2 Second Chip-Program
50 mA Typical Standby Current
0 Watts Data Retention Power
Microprocessor Microcontroller
Compatible Write Interface
through EPI Processing
High-Volume Manufacturing
Experience
32-Lead PLCC
32-Lead TSOP
random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F010 increases
memory flexibility while contributing to time and cost savings
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages Pin assignments conform to JEDEC
standards for byte-wide EPROMs
technology Advanced oxide processing an optimized tunneling structure and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs With the 12 0V V
algorithms
power consumption and immunity to noise Its 65 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 100 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel's unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to V
of quality reliability and cost-effectiveness
and float to tri-state OFF when the chip is deselected or the outputs
are disabled Data is internally latched during a write cycle
standby levels
and data is latched on the rising edge of the WE
along with the capability to perform over 100 000
electrical chip-erasure reprogram cycles These fea-
tures make the 28F010 an innovative alternative to
disk
required the 28F010's reprogrammability and non-
volatility make it the obvious and ideal replacement
for EPROM
in flash eliminate the slow disk-to-DRAM download
process This results in dramatic enhancement of
performance and substantial reduction of power
consumption
flexibility with electrical chip erasure and in-system
update capability of operating systems and applica-
tion code With updatable code system manufactur-
ers can easily accommodate last-minute changes as
revisions are made
fic reduces to a minimum and systems are instant-
on Reliability exceeds that of electromechanical
media Often in these environments power interrup-
tions force extended re-boot periods for all net-
worked terminals This mishap is no longer an issue
if boot code operating systems communication pro-
tocols and primary applications are flash-resident in
each terminal
disk for main system memory or nonvolatile backup
storage the 28F010 flash memory offers a solid
state alternative in a minimal form factor
consumption instant-on capability and allows an
``execute in place'' memory hierarchy for code and
data table reading Additionally the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail
system's life
and reprogramming ability of the 28F010 allows in-
circuit alterability this eliminates unnecessary han-
dling and less-reliable socketed connections while
adding greater test manufacture and update flexi-
bility
changes increases at higher levels of system inte-
gration
functionality prompt after-sale code updates Field
revisions to EPROM-based code requires the re-
moval of EPROM components or entire boards With
the 28F010 code updates are implemented locally
via an edge-connector or remotely over a commun-
cation link
RAM battery configuration for data accumulation
flash memory's inherent nonvolatility eliminates the
need for battery backup The concern for battery
failure no longer exists an important consideration
for portable equipment and medical instruments
both requiring continuous performance In addition
flash memory offers a considerable cost advantage
over static RAM
grammability and complete nonvolatility fit well with
data accumulation and recording needs Electrical
chip-erasure gives the designer a ``blank slate'' in
which to log or record data Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ``blank slate''
fies memory-to-processor interfacing Figure 4 de-
picts two 28F010s tied to the 80C186 system bus
The 28F010's architecture minimizes interface cir-
cuitry needed for complete in-circuit updates of
memory contents
Outline Package) is the 1 2 mm thickness With stan-
dard and reverse pin configurations TSOP reduces
the number of board layers and overall volume nec-
essary to layout multiple 28F010s TSOP is particu-
larly suited for portable equipment and applications
requiring large amounts of flash memory Figure 3
illustrates the TSOP Serpentine layout
tended cycling capability
EPROMs EEPROMs battery backed static RAM
or disk
offers designers unlimited flexibility to meet the high
standards of today's designs
