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Document Outline
- TITLE PAGE
- CONTENTS
- REVISION HISTORY
- 1.0 INTRODUCTION
- 2.0 PRODUCT DESCRIPTION
- 3.0 PRINCIPLES OF OPERATION
- 4.0 ELECTRICAL SPECIFICATIONS
- APPENDIX A: Ordering Information
- APPENDIX B: WSM Transiton Table
- APPENDIX C: Additional Information
- FIGURES
- Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System
- Figure 2. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
- Figure 3. The 40-Lead PDIP Offers the Lowest Cost Package Solution
- Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
- Figure 5. 28F002BC Internal Block Diagram
- Figure 6. 28F002BC-T Memory Map
- Figure 7. Automated Programming Flowchart
- Figure 8. Automated Block Erase Flowchart
- Figure 9. Erase Suspend/Resume Flowchart
- Figure 10. Inputs and Measurement Points
- Figure 11. Standard Test Configuration
- Figure 12. AC Waveforms for Read Operations
- Figure 13. AC Waveforms for Write and Erase Operations (WE#„Controlled Writes)
- Figure 14. Alternate AC Waveforms for Write and Erase Operations (CE#„Controlled Writes)
- TABLES
- Table 1. 28F002BC Pin Descriptions
- Table 2. 28F002BC Bus Operations
- Table 3. Command Set Codes and Corresponding Device Mode
- Table 4. Command Bus Definitions
- Table 5. Status Register Bit Definition
- Table 6. Temperature and VCC Operating Conditions
- Table 7. DC Characteristics
- Table 8. AC Characteristics: Read Only Operations
- Table 9. AC Characteristics: WE#„Controlled Write Operations
- Table 10. AC Characteristics: CE#„Controlled Write Operations
- Table 11. Erase and Program Timings (TA = +25°C)
40 ns Max. Output Enable Time
Applications
Transitions
Boot Block
Parameter Blocks
Interface
Packaging
erasure, automated write and erase operations, and a standard microprocessor interface. The 2-Mbit flash
memory enhances the Boot Block architecture by adding more density and blocks, x8 input/output control,
very high-speed, low-power, and industry-standard ROM-compatible pinout and surface mount packaging.
selectable bus operation for 8-bit applications. The 28F002BC is a 2,097,152-bit nonvolatile memory
organized as 262,144 bytes of information. It is offered in 44-lead PSOP, 40- lead PDIP and 40-lead TSOP
package, which is ideal for space-constrained portable systems or any application with board space
limitations.
byte write and block erasure. The 28F002BC provides block locations compatible with Intel's MCS®-186
family, 80286, 90860CA, and the Intel386TM, Intel486TM, Pentium®, and Pentium Pro microprocessors.
maximum access time of 80 ns, this high-performance 2-Mbit flash memory interfaces at zero wait-state to a
wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total V
low-power applications using a 3.3V supply, refer to the Intel 28F002BV-T/B
flash memory provides world-class quality, reliability, and cost-effectiveness at the 2-Mbit density.
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
obtained from:
P.O. Box 7641
Mt. Prospect, IL 60056-7641
Alternate program command (10H) removed
WSM transition table added
the 28F002BC 2-Mbit flash memory. Section 1
provides an overview of the 2-Mbit flash memory,
including applications, pinouts, and pin
descriptions. Section 2 describes the memory
organization in detail. Section 3 defines a
description of the memory's principles of
operation. Finally, Section 4 details the memory's
operating specifications.
Upgradeability
market requirements. Applications currently using
the 28F001BX and 28F002BX can migrate to this
product. Of course, both the 28F001BX and the
28F002BX devices use an 8-bit wide bus. Those
applications needing a 16-bit wide bus or lower
voltage can convert to the Smart 5 or
SmartVoltage family of flash memory products.
the 4-Mbit density. Both the 28F002BC and the
4-Mbit SmartVoltage are offered in identical
packages to make upgrade seamless. A few
simple considerations can smooth the migration
path significantly:
(this will retain boot block locking when a
4-Mbit SmartVoltage is inserted).
on occasion had to use a NOR gate (or some
other scheme) to prevent issues with floating
addresses latching incorrect data. The 28F002BC
has corrected this issue and does not need the
NOR gate. When migrating a design using the
28F002BX to the 28F002BC, the NOR gate can be
removed. When considering upgrading, packaging
is of paramount importance. Current and future
market trends indicate TSOP and PSOP as the
packages that will enable designs into the next
century.
performance, 2-Mbit (2,097,152 bit) flash memory
organized as 256 Kbytes (262,144 bytes) of 8 bits
each.
including a hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes each)
and two main blocks (one block of 98,304 bytes
and one block of 131,072 bytes). An erase
operation typically erases one of the main blocks
in 2.4 seconds and the boot or parameter blocks in
1.0 second. Each block can be independently
erased and programmed 100,000 times.
map to match the protocol of many systems,
including Intel's MCS-186 family, 80960CA, i860TM
microprocessors as well as Pentium and Pentium
Pro microprocessors. The hardware-lockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code
required for booting-up a system. When the RP#
pin is between 11.4V and 12.6V, the boot block is
unlocked and program and erase operations can
be performed. When the RP# pin is at or below
6.5V, the boot block is locked and program and
erase operations to the boot block are ignored.
interface between the microprocessor or
microcontroller and the internal operation of the
28F002BC.
and erase operations to be executed using an
industry standard two-write command sequence to
the CUI. Data writes are performed in byte
increments. Each byte in the flash memory can be
programmed independently of other memory
locations but is erased simultaneously with all
other locations within the block.
internal Write State Machine (WSM), which reports
critical information on program and/or erase
sequences.
range (0°C to +70°C), 10% V
